MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 949

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.8.1
Data buffers are used in the transmission and reception of Ethernet frames (see
encapsulate all information necessary for the eTSEC to transmit or receive an Ethernet frame. Within each
data BD there is a status field, a data length field, and a data pointer. The BD completely describes an
Ethernet packet by centralizing status information for the data packet in the status field of the BD and by
containing a data BD pointer to the location of the data buffer. Software is responsible for setting up the
BDs in memory. Because of pre-fetching, a minimum of four buffer descriptors per ring are required. This
applies to both the transmit and the receive descriptor rings. Transmit rings are limited to a maximum size
of 65536 BDs due to BD and frame data prefetching. Software also must have the data pointer pointing to
a legal memory location. Within the status field, there exists an ownership bit which defines the current
state of the buffer (pointed to by the data pointer). Other bits in the status field of the buffer descriptor are
used to communicate status/control information between the eTSEC and the software driver.
Because there is no next BD pointer in the transmit/receive BD (see
sequentially in memory. The eTSEC increments the current BD location appropriately to the next BD
location to be processed. There is a wrap bit in the last BD that informs the eTSEC to loop back to the
beginning of the BD chain. Software must initialize the TBASE and RBASE registers that point to the
beginning transmit and receive BDs for eTSEC.
Freescale Semiconductor
Data Buffer Descriptors
Memory Map
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RxBD Table
TxBD Table
(RBASE n )
(TBASE n )
Pointer
Pointer
Figure 14-154. Example of eTSEC Memory Structure for BDs
System Memory
Table for Ring n
Table for Ring n
Rx Buffer
Tx Buffer
RxBD
TxBD
Figure
Status & Control
Status & Control
Buffer Pointer
Buffer Pointer
Enhanced Three-Speed Ethernet Controllers
Data Length
Data Length
Tx Buffer Descriptors
Rx Buffer Descriptors
14-155), all BDs must reside
Figure
14-154). Data BDs
14-201