MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 484

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_1020
Reset
Security Engine (SEC) 3.0
10.5.4.3
The ICR provides a means of clearing the interrupt status register (ISR). Setting an ICR bit clears the
corresponding bit in the ISR, and negates the interrupt output signal (assuming that particular ISR bit is
the only interrupt source). When set, an ICR bit is cleared automatically on the following cycle.
10.5.4.4
The read-only ID register, displayed in
register (see Section 10.5.4.5 below). This register provides the IP block revision information at a legacy
location for software convenience.
10.5.4.5
The read-only IP block revision register, displayed in
identifies the version of the SEC.
10-54
Offset 0x 3_1BF8
Reset
W
R
W
R
0
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Interrupt Clear Register (ICR)
ID Register
IP Block Revision Register
If the cause of an interrupt is not removed, then the ISR bit is set (and
corresponding interrupt output signal asserted) a few cycles after it has been
cleared using the ICR.
For this reason, the ICR is ineffective in clearing the RNG Done bit (bit 47)
in the ISR. The user should use the IER to mask the RNG Done interrupt.
To determine whether a descriptor-based RNG request is complete, the user
should rely on Channel Done interrupts.
IP_ID
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-19. IP Block Revision Register
IP_MJ
Figure
Figure 10-18. ID Register
IP_MN
10-18, contains the same value as the IP block revision
NOTE
All zeros
31 32
Figure
ID
—
10-19, contains a 64-bit value that uniquely
IP_INT
Freescale Semiconductor
—
Access: Read only
Access: Read only
IP_CFG
63
63