MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1145

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8.1.6
The class code register, shown in
0x0B), sub-class (offset 0x0A), and programming interface (offset 0x09)—that indicate the basic
functionality of the function.
.
17.3.8.1.7
The cache line size register, shown in
2.3); it is not used for PCI Express device functionality.
Table 17-43
Freescale Semiconductor
Table 17-42
Offset 0x09
Reset 0
Offset 0x0C
Reset
23–16 Base Class 0x0B—Processor
15–8
Bits
7–0 Programming
Bits
7–0
W
R
W
R
23
Sub-Class
Interface
Cache Line
Name
0
Name
7
describes the cache line size register.
describes the class code register fields.
Size
PCI Express Class Code Register—Offset 0x09
PCI Express Cache Line Size Register—Offset 0x0C
0
Table 17-43. PCI Express Bus Cache Line Size Register Field Descriptions
Base Class
0x20—PowerPC
0x00—RC mode
0x01—EP mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Represents the cache line size of the processor in terms of 32-bit words (8 32-bit words = 32 bytes).
Note that for PCI Express operation this register is ignored.
Table 17-42. PCI Express Class Code Register Field Descriptions
1
Figure 17-43. PCI Express Bus Cache Line Size Register
0
Figure 17-42. PCI Express Class Code Register
1
Figure
16
1
Figure
17-42, is comprised of three single-byte fields—base class (offset
15
0
0
17-43, is provided for legacy compatibility purposes (PCI
1
Cache Line Size
Sub-Class
All zeros
0
Description
0
Description
0
0
8
0
7
0x00 RC mode; 0x01 EP mode
Programming Interface
PCI Express Interface Controller
Access: Read/Write
Access: Read only
0
17-49
0