MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 816

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.3.9
The MRBLR register is written by the user. It informs the eTSEC how much space is in the receive buffer
pointed to by the RxBD.
14.5.3.3.10 Receive Data Buffer Pointer High Register (RBDBPH)
The RBDBPH register is written by the user with the most significant address bits common to all RxBD
buffer addresses, RxBD[Data Buffer Pointer]. As a consequence, Rx buffers must be placed in a 4 Gbyte
segment of memory whose base address is prefixed by the bits in RBDBPH. The RxBD ring itself can
14-68
1
1100 0–31
1101 0–31
1110 0–15
1111 0–15
PID
16–25
26–31
0–15
\\
Bits
PID is the property identifier field of the filer table control entry (see RQFCR[PID]) at the same index.
Offset eTSEC1:0x2_4340;
Reset
1
16–31
16–31
W
R
Bit
Name
MRBL Maximum receive buffer length. MRBL is the number of bytes that the eTSEC receiver writes to the receive
eTSEC3:0x2_6340
0
—
—
Name
DPT
SPT
DIA
SIA
—
—
Maximum Receive Buffer Length Register (MRBLR)
Reserved
buffer. The MRBL register is written by the user with a multiple of 64 for all modes. The eTSEC can write fewer
bytes to the buffer than the value set in MRBL if a condition such as an error or end-of-frame occurs, but it
never exceeds the MRBL value; therefore, user-supplied buffers must be at least as large as the MRBL. MRBL
must be set, together with the number of buffer descriptors, to ensure adequate space for received frames.
See
To ensure that MRBL is a multiple of 64, these bits are reserved and should be cleared.
Section 14.5.3.5.5, “Maximum Frame Length Register
Destination IP address. If an IPv4 header was found, this is the entire destination address. If an IPv6
header was found, this is the 32 most significant bits of the 128-bit destination address. This value
defaults to 0x0000_0000 if no IP header appeared.
Source IP address. If an IPv4 header was found, this is the entire source address. If an IPv6 header was
found, this is the 32 most significant bits of the 128-bit source address. This value defaults to
0x0000_0000 if no IP header appeared.
Reserved, should be written with zero.
Destination port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP
headers were recognized.
Reserved, should be written with zero.
Source port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP headers
were recognized.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-33
Table 14-36. RQFPR Field Descriptions (continued)
—
Figure 14-33. MRBLR Register Definition
Table 14-37. MRBLR Field Descriptions
describes the definition for the MRBLR.
All zeros
15 16
Description
Description
(MAXFRM),” for further discussion.
MRBL
Freescale Semiconductor
25 26
Access: Read/Write
—
31