MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 629

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.1.7
The UAFRs give software the ability to gate off the baud clock and write to both UART0/UART1 registers
simultaneously with the same write operation.
Figure 12-9
Table 12-12
12.3.1.8
The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB],
which controls the ability to access the divisor latch least and most significant bit registers and the alternate
function register.
Freescale Semiconductor
Bits
Bits
0–5
5
6
7
6
7
Offset UART0: 0x502, UART1: 0x602
Reset
Name
Name
RFR
TFR
FEN
CW
BO
W
—
R
shows the bits in the UAFRs.
describes the fields of the UAFRs.
Transmitter FIFO reset
0 No action
1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
Receiver FIFO reset
0 No action
1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
FIFO enable
0 FIFOs are disabled and cleared
1 Enables the transmitter and receiver FIFOs
Reserved.
Baud clock select.
0 The baud clock is not gated off.
1 The baud clock is gated off.
Concurrent write enable.
0 Disables writing to both UART0 and UART1
1 Enables concurrent writes to corresponding UART registers. A write to a register in UART0 is also a write
Alternate Function Registers (UAFR n ) (ULCR[DLAB] = 1)
Line Control Registers (ULCR n )
to the corresponding register in UART1 and vice versa. The user needs to ensure that the LCR[DLAB] of
both UARTs are in the same state before executing a concurrent write to register addresses 0x n 00, 0x n 01
and 0x n 02, where n is the offset of the corresponding UART.
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 12-11. UFCR Field Descriptions (continued)
Figure 12-9. Alternate Function Register (UAFR)
Table 12-12. UAFR Field Descriptions
—
All zeros
Description
Description
5
BO
Access: Read/Write
6
CW
7
DUART
12-11