MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 691

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Figure 13-35

can configure ORn[ACS] to specify LCS to meet this requirement. Generally, the attributes for the

memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR

and SETA fields.

The basic GPCM read timing parameters that may be set by the ORn attributes are shown in

The read access cycle commences upon latching of the memory address (LALE negated), and concludes

when LBCTL returns high to turn the local bus around for a subsequent address phase. Read data is

captured by eLBC on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases

before the end of the read access to provide additional hold time for the external memory.

Freescale Semiconductor

shows LCS as defined by the setup time required between the address lines and CE. The user

GPCM Read Signal Timing

eLBC in GPCM

Figure 13-35. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0)

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 13-34. Enhanced Local Bus to GPCM Device Interface

Latched Address

Memory/Peripheral

Enhanced Local Bus Controller