MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 326

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-37
8.4.1.32
The memory data path error injection mask low register is shown in
Table 8-38
8.4.1.33
The memory data path error injection mask ECC register, shown in
enables errors to be written to ECC memory, and allows the ECC byte to mirror the most significant data
byte. In addition, a single address parity error may be injected through this register.
8-52
0–31
0–31
Offset 0xE08
Bits
Bits
Reset
Offset 0xE04
Reset
W
R
W
Figure 8-33. Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)
R
0
Name
Name
EIMH Error injection mask high data path. Used to test ECC by forcing errors on the high word of the data path.
EIML
0
describes the DATA_ERR_INJECT_HI fields.
describes the DATA_ERR_INJECT_LO fields.
Figure 8-34. Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)
Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)
Memory Data Path Error Injection Mask ECC (ERR_INJECT)
Setting a bit causes the corresponding data path bit to be inverted on memory bus writes.
Error injection mask low data path. Used to test ECC by forcing errors on the low word of the data path. Setting
a bit causes the corresponding data path bit to be inverted on memory bus writes.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-38. DATA_ERR_INJECT_LO Field Descriptions
Table 8-37. DATA_ERR_INJECT_HI Field Descriptions
—
14
APIEN
15
All zeros
All zeros
EIML
Description
Description
16
—
Figure
Figure
21
EMB EIEN
22
8-34, sets the ECC mask,
8-33.
23
24
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
EEIM
31
31