MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1595

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.3.1.3
The watchpoint monitor address mask register (WMAMR) shown in
address in the WMAR.
Table 25-10
25.3.1.4
The watchpoint monitor transaction mask register (WMTMR), shown in
transaction types to monitor. WMTMR allows users to qualify watchpoint events specifically with any
combination of transaction types. As shown in
transaction types; one for each interface. Setting a bit enables watchpoint monitoring for the corresponding
transaction types.
Because the supported transaction types vary by interface, the type designated by a WMTMR field also
depends on the interface specified by WMCR1[IFSEL].
each WMTMR bit by interface.
Freescale Semiconductor
Offset 0x014
Reset
Offset 0x018
Reset
0–31
Bits
0–31
Bits
W
W
R
R
0
0
WMAM Watchpoint monitor address mask. A value of zero masks the address comparison for the corresponding
Name
Name
WMA
describes the WMAMR fields.
Watchpoint Monitor Transaction Mask Register (WMTMR)
Watchpoint Monitor Address Mask Register (WMAMR)
address bit. These bits only mask the address bits generated by the hardware, but do not affect the bits
specified in WMAR. A bit that is masked from the comparison should be set to 0 in WMAR.
Figure 25-6. Watchpoint Monitor Transaction Mask Register (WMTMR)
Watchpoint monitor address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 25-5. Watchpoint Monitor Address Mask Register (WMAMR)
Table 25-10. WMAMR Field Descriptions
Table 25-9. WMAR Field Descriptions
Table
All zeros
All zeros
WMAM
WMTM
25-11, each bit represents as many as four separate
Table 25-12
Description
Description
Figure 25-5
lists transaction types associated with
Figure
Debug Features and Watchpoint Facility
contains the mask for the
25-6, specifies which
Access: Read/Write
Access: Read/Write
25-13
31
31