MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1509

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x070
Reset
Reset
Note that bits with a reset value of n depend on the state of POR configuration signals at reset.
All functional blocks are enabled after reset; unneeded blocks can be disabled to reduce power
consumption. Blocks disabled by DEVDISR must not be re-enabled without a hard reset.
“Shutting Down Unused
Table 23-13
Freescale Semiconductor
W
W
R
R
DDR E500
PCI
16
n
0
0
Bits
0
1
2
3
4
5
6
7
8
—
17
0
0
1
describes DEVDISR fields.
PCIE1 — ELBC PCIE2 PCIE3
TB
18
n
0
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCIE1
PCIE2
PCIE3
Name
ELBC
USB1
SEC
PCI
—
—
19
— SATA2 DMA
0
0
3
Blocks,” has more information on the use of DEVDISR.
20
0
n
4
Figure 23-10. Device Disable Register (DEVDISR)
PCI controller disable.
0 PCI controller enable
1 PCI controller disable
Reserved. Should be cleared.
PCI Express 1 controller disable.
0 PCI Express 1 controller enable
1 PCI Express 1 controller disable
Reserved. Should be cleared.
Enhanced local bus controller disable.
0 Enhanced local bus controller enable
1 Enhanced local bus controller disable
PCI Express 2 controller disable.
0 PCI Express 2 controller enable
1 PCI Express 2 controller disable
PCI Express 3 controller disable.
0 PCI Express 3 controller enable
1 PCI Express 3 controller disable
Security disable controller.
0 Security enable
1 Security disable
USB 1 controller disable.
0 USB 1 enable
1 USB 1 disable
Table 23-13. DEVDISR Field Descriptions
21
n
0
5
—
22
n
0
6
SRDS2 eTSEC1
SEC
23
0
n
7
USB1
24
0
0
8
Description
USB2
—
25
9
0
0
eTSEC3
USB3
10
26
0
0
L2 eSDHC SATA1
11
27
0
0
—
12
28
0
0
I2C
13
29
n
0
Section 23.5.1.5,
Access: Read/Write
DUART SRDS1
Global Utilities
—
14
30
0
0
23-17
SPI
15
31
0
n