MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1383

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5.4.3
DWords 3–6 manage the state of the transfer.
Freescale Semiconductor
15–12
31–16
29–26
25–16
11–8
15–8
15–8
Bits
Bits
Bits
6–0
7–0
31
30
7
µFrame C-mask Split completion mask. This field (along with the Active and SplitX- state fields in the status byte) is
Device Address Selects the specific device serving as the data source or sink.
µFrame S-mask Split start mask. This field (along with the Active and SplitX-state fields in the Status byte) is used
Total Bytes to
C-prog-mask
Transfer
µFrame
Name
Name
EndPt
Name
ioc
—
siTD Transfer State
P
—
—
—
Table 21-45. Endpoint and Transaction Translator Characteristics (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interrupt on complete
0 Do not interrupt when transaction is complete.
1 Do interrupt when transaction is complete. When the host controller determines that the split
Page select. Indicates which data page pointer should be concatenated with the CurrentOffset field
to construct a data buffer pointer
0 Selects Page 0 pointer
1 Selects Page 1 pointer
The host controller is not required to write this field back when the siTD is retired (Active bit
transitioned from a one to a zero).
Reserved, should be cleared. This field reserved for future use and should be cleared.
This field is initialized by software to the total number of bytes expected in this transfer. Maximum
value is 1023 (3FFh)
Split complete progress mask. This field is used by the host controller to record which split-completes
have been executed.
Reserved, should be cleared. Field reserved and should be cleared.
Endpoint Number. Selects the particular endpoint number on the device serving as the data source
or sink.
Reserved, should be cleared. Bit is reserved for future use. It should be cleared.
Reserved, should be cleared. This field reserved for future use. It should be cleared.
used to determine during which micro-frames the host controller should execute complete-split
transactions. When the criteria for using this field is met, an all-zeros value has undefined behavior.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame C-Mask field is
a one, this siTD is a candidate for transaction execution. There may be more than one bit in this
mask set.
to determine during which micro-frames the host controller should execute start-split transactions.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame S-mask field is
a one, then this siTD is a candidate for transaction execution. An all zeros value in this field, in
combination with existing periodic frame list has undefined results.
transaction has completed it will assert a hardware interrupt at the next interrupt threshold.
Table 21-47. siTD Transfer Status and Control
Table 21-46. Micro-Frame Schedule Control
Description
Description
Description
Universal Serial Bus Interfaces
21-49