MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1423

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.12.2.2 Host Controller Operational Model for FSTNs
The FSTN data structure is used to manage Low/Full-speed interrupt queue heads that need to be reached
from consecutive frame list locations (that is, boundary cases 2a through 2c). An FSTN is essentially a
back pointer, similar in intent to the back pointer field in the siTD data structure.
This feature provides software a simple primitive to save a schedule position, redirect the host controller
to traverse the necessary queue heads in the previous frame, then restore the original schedule position and
complete normal traversal.
There are four components to the use of FSTNs:
When the host controller encounters an FSTN during micro-frames 2 through 7 it simply follows the node's
Normal Path Link Pointer to access the next schedule data structure. Note that the FSTN's Normal Path
Link Pointer[T] bit may set, which the host controller must interpret as the end of periodic list mark.
When the host controller encounters a Save-Place FSTN in micro-frames 0 or 1, it saves the value of the
Normal Path Link Pointer and sets an internal flag indicating that it is executing in Recovery Path mode.
Recovery Path mode modifies the host controller's rules for how it traverses the schedule and limits which
data structures are considered for execution of bus transactions. The host controller continues executing in
Recovery Path mode until it encounters a Restore FSTN or it determines that it has reached the end of the
micro-frame.
The rules for schedule traversal and limited execution while in Recovery Path mode are:
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Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the
micro-frames (within an H-Frame) that the host controller should execute complete-split
transactions. The interpretation of this field is always qualified by the value of the SplitXState bit
in the Status field of the queue head. For example, referring to
would have a value of 0b0001_1100 indicating that if the queue head is traversed by the host
controller, and the SplitXState indicates Do_Complete, and the current micro-frame as indicated
by FRINDEX[2–0] is 2, 3, or 4, then execute a complete-split transaction. It is software's
responsibility to ensure that the translation between H-Frames and B-Frames is correctly
performed when setting bits in S-mask and C-mask.
FSTN data structure, defined in
A Save Place indicator; this is always an FSTN with its Back Path Link Pointer[T] bit cleared.
A Restore indicator; this is always an FSTN with its Back Path Link Pointer[T] bit set.
Host controller FSTN traversal rules.
Always follow the Normal Path Link Pointer when it encounters an FSTN that is a Save-Place
indicator. The host controller must not recursively follow Save-Place FSTNs. Therefore, while
executing in Recovery Path mode, it must never follow an FSTN's Back Path Link Pointer.
Do not process an siTD or iTD data structure; simply follow its Next Link Pointer.
Do not process a QH (Queue Head) whose EPS field indicates a high-speed device; simply follow
its Horizontal Link Pointer.
When a QH's EPS field indicates a Full/Low-speed device, the host controller only considers it for
execution if its SplitXState is DoComplete (note: this applies whether the PID Code indicates an
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 21.5.7, “Periodic Frame Span Traversal Node (FSTN).”
Figure
21-52, case one, the C-mask
Universal Serial Bus Interfaces
21-89